The present disclosure relates to power supply interconnect structures including interconnect layers having a limitation on the lengths or areas of interconnects, and semiconductor devices having the power supply interconnect structures.
Conventionally, the layout of a semiconductor integrated circuit is designed in the following manner. Logic elements which are constituent elements of the semiconductor integrated circuit are mounted on a chip based on connection between each logic element, a power supply interconnect for power supply is connected to each logic element, and signal terminals of the logic elements are connected by signal interconnects to provide the intended logic function. In particular, conventionally, in order to supply a stable current, the power supply interconnects are typically connected so that some of the power supply interconnects having the same potential are arranged in a mesh, equally spaced, and have equal widths on the entire chip surface (Japanese Patent Publication No. 2000-11011).
In recent years, the integration density and chip size of a semiconductor integrated circuit have increased. Therefore, the amount of power consumed by the semiconductor integrated circuit has also tended to increase. Therefore, in order to stably supply power to the semiconductor integrated circuit, a power supply interconnect for supplying power is adapted to have an interconnect structure having a wider interconnect width and a longer interconnect length in an interconnect layer having a low resistance. However, when a single power supply interconnect which connects one end to another end of a chip or one end to another end of a range within which power is supplied at the same potential, is too long to be implemented from the point of view of ease of manufacture, the power supply interconnect needs to be limited to less than a predetermined length or area.
FIG. 1 is a plan view of the power supply interconnect structure described above. For example, the power supply interconnect structure includes three layers, i.e., a first, a second, and a third interconnect layer. The three layers are assumed to be equally spaced and have equal widths. In FIG. 1, a reference numeral 100 indicates a voltage supply, a reference numeral 101 indicates a measurement point, reference numerals 102-105 indicate power supply interconnects in the first interconnect layer, reference numerals 106-110 indicate power supply interconnects in the second interconnect layer, reference numerals 111-114 indicate power supply interconnects in the third interconnect layer, reference numerals 115-134 indicate vias which connect the first and second interconnect layers together, and reference numerals 135-154 indicate vias which connect the second and third interconnect layers together. The power supply interconnects are all assumed to have the same potential.
For ease of description, it is assumed that the resistance value per unit mesh length of the first interconnect layer is 20Ω, the resistance value of the second interconnect layer is negligible, and the resistance value per unit mesh length of the third interconnect layer is 100Ω. It is also assumed that the resistance values of the vias 115-134 connecting the first and second interconnect layers together and the vias 135-154 connecting the second and third interconnect layers together are negligible.
FIG. 2 is a plan view of a power supply interconnect structure in which there is a limitation on the lengths of interconnects and areas occupied by the interconnects (hereinafter referred to as “the areas of the interconnects” or “the interconnect areas”) from the point of view of ease of manufacture as described above. In FIG. 2, for example, in the power supply interconnect structure, interconnects are limited to less than a predetermined length in only the first interconnect layer. In FIG. 2, a reference numeral 200 indicates a voltage supply, a reference numeral 201 indicates a measurement point, reference numerals 202-205 and 255-258 indicate power supply interconnects in the first interconnect layer, reference numerals 206-210 indicate power supply interconnects in the second interconnect layer, reference numerals 211-214 indicate power supply interconnects in the third interconnect layer, reference numerals 215-234 indicate vias which connect the first and second interconnect layers together, and reference numerals 235-254 indicate vias which connect the second and third interconnect layers together. Reference numerals 259 and 260 indicate empty spaces between segments of power supply interconnects between vias in the first interconnect layer in which there is a limitation on the lengths and areas of the interconnects.
Note that, here, it is assumed that the voltage supply 100 and the measurement point 101 of FIG. 1 and the voltage supply 200 and the measurement point 201 of FIG. 2 are located at the same positions, respectively.
FIG. 3 is a plan view of the same power supply interconnect structure as that of FIG. 1. In FIG. 3, a reference numeral 300 indicates a voltage supply, which is assumed to be the same as the voltage supply 100 of FIG. 1. A reference numeral 301 indicates a measurement point, which is assumed to be the same as that of the measurement point 101 of FIG. 1. Reference numerals 302-305 indicate power supply interconnects in the first interconnect layer, which are assumed to be the same as the power supply interconnects 102-105 of FIG. 1. Reference numerals 306 and 307 indicates power supply interconnects in the second interconnect layer, which are assumed to be the same as the power supply interconnects 106 and 107 of FIG. 1. Reference numerals 311-314 indicate power supply interconnects in the third interconnect layer, which are assumed to be the same as the power supply interconnects 111-114 of FIG. 1. A reference numeral 315 indicates a calculation range within which calculation is performed using an expression described below.
FIG. 4 is a plan view of a power supply interconnect structure in which there is a limitation on the lengths and areas of interconnects from the point of view of ease of manufacture as described in FIG. 2, as viewed from above. In FIG. 4, a reference numeral 400 indicates a voltage supply, which is assumed to be the same as the voltage supply 200 of FIG. 2. A reference numeral 401 indicates a measurement point, which is assumed to be the same as the measurement point 201 of FIG. 2. Reference numerals 402-405 indicate power supply interconnects in the first interconnect layer, which are assumed to be the same as the power supply interconnects 202-205 of FIG. 2. Reference numerals 406 and 407 indicate power supply interconnects in the second interconnect layer, which are assumed to be the same as the power supply interconnects 206 and 207 of FIG. 2. Reference numerals 411-414 indicate power supply interconnects in the third interconnect layer, which are assumed to be the same as the power supply interconnects 211-214 of FIG. 2. Reference numerals 415-418 indicate calculation ranges within which calculation is performed using an expression described below.
Firstly, an influence of the limitation on the lengths and areas of interconnects on a resistance value will be described with reference to FIGS. 3 and 4. The voltage supply 300 and the measurement point 301 of FIG. 3 and the voltage supply 400 and the measurement point 401 of FIG. 4 are assumed to be located at the same positions, respectively, and are also assumed to be located at the same positions as those of the voltage supply 100 and the measurement point 101 of FIG. 1 and the voltage supply 200 and the measurement point 201 of FIG. 2, respectively. Moreover, in FIGS. 3 and 4, as is similar to FIGS. 1 and 2, the power supply interconnect structure is assumed to include three layers, i.e., a first, a second, and a third interconnect layer, which are equally spaced and have equal widths.
A resistance value from the voltage supply 300 to the measurement point 301 is compared with a resistance value from the voltage supply 400 to the measurement point 401.
Firstly, assuming that there is not a limitation on the lengths and areas of interconnects in FIG. 3, a resistance value within the calculation range indicated by the reference numeral 315 will be described. Because it is assumed that the resistance value of the second interconnect layer and the vias is negligible, the resistance value within the calculation range 315 is calculated, taking only the first and third interconnect layers into account.
The resistance value R1 of the first interconnect layer is obtained as follows. There are a total of the four power supply interconnects 302-305 in the first interconnect layer within the calculation range 315. The power supply interconnects 302-305 are connected together in parallel, and the resistance value R1 of the first interconnect layer is calculated by:R1=1/(1/20+1/20+1/20+1/20)=5 (Ω)  (1)
Next, the resistance value R3 of the third interconnect layer is obtained as follows. There are a total of the four power supply interconnects 311-314 in the third interconnect layer within the calculation range 315. The power supply interconnects 311-314 are connected together in parallel, and the resistance value R3 of the third interconnect layer is calculated by:R3=1/(1/100+1/100+1/100+1/100)=25 (Ω)  (2)
The resistance value from the voltage supply 300 to the measurement point 301 is calculated based on the resistance values R1 and R3 as follows. Because it is assumed as described above in FIG. 1 that the interconnects in the first, second, and third interconnect layers are equally spaced and have equal widths, the resistance value R_SUM from the voltage supply 300 to the measurement point 301 is obtained by:
                                                        R_SUM              =                            ⁢                                                1                  /                                      (                                                                                            1                          /                          R                                                ⁢                                                                                                  ⁢                        1                                            +                                                                        1                          /                          R                                                ⁢                                                                                                  ⁢                        3                                                              )                                                  +                                  1                  /                                      (                                                                                            1                          /                          R                                                ⁢                                                                                                  ⁢                        1                                            +                                                                        1                          /                          R                                                ⁢                                                                                                  ⁢                        3                                                              )                                                  +                                                                                                      ⁢                                                1                  /                                      (                                                                                            1                          /                          R                                                ⁢                                                                                                  ⁢                        1                                            +                                                                        1                          /                          R                                                ⁢                                                                                                  ⁢                        3                                                              )                                                  +                                  1                  /                                      (                                                                                            1                          /                          R                                                ⁢                                                                                                  ⁢                        1                                            +                                                                        1                          /                          R                                                ⁢                                                                                                  ⁢                        3                                                              )                                                                                                                          =                            ⁢                              16.7                ⁢                                  (                  Ω                  )                                                                                        (        3        )            
Next, assuming that there is a limitation on the lengths and areas of interconnects, a resistance value will be described with reference to FIG. 4. Also in FIG. 4, as is similar to FIG. 3, because it is assumed that the resistance value of the second interconnect layer and the vias is negligible, the resistance value from the voltage supply 400 to the measurement point 401 is calculated, taking only the first and third interconnect layers into account.
Initially, the resistance value R1′ of the first interconnect layer is obtained as follows. As is different from the case of FIG. 3, in FIG. 4, there is no interconnect in the first interconnect layer within the calculation range 417. There are a total of the four power supply interconnects 402-405 in the first interconnect layer within the calculation ranges 415, 416, and 418, and the power supply interconnects 402-405 are connected together in parallel. Therefore, the resistance value R1′ of the first interconnect layer is obtained, as is similar to Expression 1 used for FIG. 3, by:R1′=1/(1/20+1/20+1/20+1/20)=5 (Ω)  (4)
Note that because there is no power interconnect in the first interconnect layer within the calculation range 417, the resistance value of the first interconnect layer is zero.
Next, the resistance value R3′ of the third interconnect layer is obtained as follows. There are a total of the four power supply interconnects 411-414 in the third interconnect layer within the calculation ranges 415-418. The power supply interconnects 411-414 are connected together in parallel. Therefore, the resistance value R3′ of the third interconnect layer is calculated, as is similar to the case of FIG. 3, by:R3′=1/(1/100+1/100+1/100+1/100)=25 (Ω)  (5)
Therefore, the resistance value R_SUM′ from the voltage supply 400 to the measurement point 401 is calculated by:
                                                                        R_SUM                ′                            =                            ⁢                                                1                  /                                      (                                                                                            1                          /                          R                                                ⁢                                                                                                  ⁢                        1                                            +                                                                        1                          /                          R                                                ⁢                                                                                                  ⁢                        3                                                              )                                                  +                                  1                  /                                      (                                                                                            1                          /                          R                                                ⁢                                                                                                  ⁢                        1                                            +                                                                        1                          /                          R                                                ⁢                                                                                                  ⁢                        3                                                              )                                                  +                                                                                                      ⁢                                                R                  ⁢                                                                          ⁢                  3                                +                                  1                  /                                      (                                                                                            1                          /                          R                                                ⁢                                                                                                  ⁢                        1                                            +                                                                        1                          /                          R                                                ⁢                                                                                                  ⁢                        3                                                              )                                                                                                                          =                            ⁢                              37.5                ⁢                                  (                  Ω                  )                                                                                        (        6        )            
Thus, in FIG. 4 where there is a limitation on the lengths and areas of interconnects in FIG. 4, the resistance value is higher than that of FIG. 3. Although it is assumed in the above example that the interconnect layers have different resistance values, a similar effect is obtained even when the interconnect layers have the same resistance value or when the second interconnect layer has a non-negligible resistance.
Next, an influence of the limitation on the lengths and areas of interconnects on a voltage drop will be described with reference to FIGS. 3 and 4.
Here, a voltage drop at any point is represented by:voltage drop=VDD−Σ(Ia×Ra)  (7)where VDD is the voltage value of the voltage supply, Ia is a current value at any measurement point, and Ra is a resistance value between any two points.
Here, it is assumed that there are cells at only the measurement point 301 of FIG. 3 and the measurement point 401 of FIG. 4, and currents at both the measurement points 301 and 401 are a constant current supply. Expression 7 is also represented by:voltage drop=VDD−I×R_SUM  (8)where I is a current value at any measurement point, and R_SUM is a resistance value from the voltage supply to the measurement point.
In Expression 8, if it is assumed that the measurement point 301 of FIG. 3 and the measurement point 401 of FIG. 4 have the same current value, the influence on the voltage drop in each of FIGS. 3 and 4 varies depending on the resistance value from the voltage supply to any measurement point. As described above, the resistance value in FIG. 4 where there is a limitation on the lengths and areas of interconnects is higher than that in FIG. 3 where there is not a limitation on the lengths and areas of interconnects. As can be seen from the foregoing description, the voltage drop at the measurement point 401 in FIG. 4 where there is a limitation on the lengths and areas of interconnects is larger than the voltage drop at the measurement point 301 in FIG. 3 where there is not a limitation on the lengths and areas of interconnects.
Therefore, when there is a limitation on the lengths and areas of power supply interconnects, an additional problem arises, i.e., the influence on the voltage drop increases.
In general, the influence on the voltage drop is taken into account when a delay is calculated in the design of a semiconductor integrated circuit, and therefore, the increase in the voltage drop interferes with the enhancement of performance of the semiconductor integrated circuit. While the lengths and areas of interconnects need to be limited to less than predetermined values from the point of view of ease of manufacture as shown in FIG. 2, the voltage drop needs to be reduced to the extent possible for the above reasons.